This invention relates generally to signal processors and more particularly to signal processors which are used in light-weight radar-guided missiles to process radar return signals using digital Fast Fourier Transform (FFT) techniques in order to analyze the frequency spectrum of such radar return signals.
As is known in the art, in a ground based radar system detection of a target in a noise or clutter environment may be obtained by discriminating between the Doppler frequency of the target and the Doppler frequency of the noise or clutter. One technique which may be used in such frequency discrimination is through the use of a Fast Fourier Transform (FFT) processor. In particular, generally the video output of the radar receiver is sampled and converted into corresponding digital words. The digital words are processed in parallel form, the number of bits in each one of such digital words being related to the dynamic range of the signal to be analyzed. The Fast Fourier Transform processor processes these digital words to produce a set of digital words which correspond to discrete frequency components of the frequency spectrum of the received radar signals. A digital computer may then be included to process the output of the Fast Fourier Transform (FFT) processor and thereby provide signals which enable the ground based radar system to "frequency" track a target, such target being selected in accordance with its Doppler frequency as analyzed by the FFT processor.
While such FFT processor may theoretically be used in a small, lightweight radar-guided missile, because of the restriction on space and weight in such missile, and in order to provide maximum signal processing capability within such a missile, it is necessary that the number of components used in "on board" signal processing equipment be minimized. In this regard, the Fast Fourier Transform (FFT) processor may generally be characterized as a digital processor which repetitively performs the basic computations: EQU AW+B; AW-B,
where A and B are complex digital words, each initially associated with a different one of N digital samples, generally of the radar video signal the frequency spectrum of which is to be analyzed, and W is a complex digital word which serves as a weighting coefficient. The above computations would be performed by processing such digital words in parallel form, as mentioned above, using a complex multiplier to perform the AW portion of the calculation, a storage means for storing such portion of the calculation, and a complex parallel adder and subtractor for adding and subtracting the stored portion of the calculation to and from, respectively, the B portion of the calculation. While such complex adder and subtractor may adequately perform the required calculations, in a radar guided missile application where the number of bits in each digital word, which is presented in parallel form, may be in the order of 16 to 32 bits, the complex adder and subtractor increase the size and complexity of the FFT processor such that its use in the missile may be prevented.